In the era of PCIe 5.0 and the emerging PCIe 6.0 standards, maintaining signal integrity (SI) across high-density interconnects like SlimSAS (SFF-8654) has become a primary bottleneck for hardware engineers. At Nyquist frequencies of 16 GHz (for 32GT/s), the margin for error effectively vanishes.
This article dissects the dual-threat of dielectric absorption and impedance mismatch within SlimSAS assemblies.
1. The Physics of Attenuation at 16 GHz
Signal degradation in a SlimSAS link is primarily governed by the total insertion loss ($IL_{total}$), which is the summation of conductor loss and dielectric loss.
Dielectric Loss Tangent ($\tan \delta$)
At 32GT/s, the dielectric loss becomes the dominant factor over skin effect. The loss per inch can be modeled by:
$$A_{d} \approx 2.32 \cdot f \cdot \tan \delta \cdot \sqrt{\epsilon_{r}}$$
Where:
$f$ is the frequency in GHz.
$\tan \delta$ is the dissipation factor of the PCB/cable laminate.
$\epsilon_{r}$ is the relative permittivity.
For standard FR4, the attenuation at 16 GHz is prohibitive. High-speed SlimSAS implementations require Ultra-Low Loss (ULL) materials like Megtron 6 or Tachyon 100G to keep the budget within the -36 dB limit defined by the PCIe 5.0 specification for the entire channel.
2. Impedance Discontinuity: The Connector Interface
The SlimSAS connector is a high-density interface where the geometry changes abruptly. This creates a "capacitive bump" or "inductive spike" in the Time Domain Reflectometry (TDR) profile.
The 85 $\Omega$ vs. 100 $\Omega$ Conflict
While many legacy systems use 100 $\Omega$ differential impedance, PCIe 5.0 leans toward 85 $\Omega$ to reduce EMI and improve routing density. A common failure point in SlimSAS links is the mismatch between the 85 $\Omega$ cable and a 92¨C95 $\Omega$ connector footprint, leading to reflections ($S_{11}$) that manifest as eye-closure.
3. Empirical Test Data: SlimSAS Twinaxial Assembly
The following data represents a typical 1-meter SlimSAS-to-SlimSAS (8nd) passive cable assembly test under laboratory conditions.
| Frequency (GHz) | Insertion Loss (dB) | Return Loss (dB) | Near-End Crosstalk (dB) |
| 4.0 (PCIe 3.0) | -2.1 | -18.5 | -42 |
| 8.0 (PCIe 4.0) | -4.8 | -15.2 | -38 |
| 16.0 (PCIe 5.0) | -9.4 | -12.1 | -31 |
| 32.0 (PCIe 6.0) | -18.7 | -8.4 | -24 |
Analysis:
At 16 GHz, we observe a sharp decline in Return Loss. Once $S_{11}$ rises above -10 dB, the resulting standing waves significantly increase the Total Jitter (Tj), making it difficult for the Receiver (Rx) Clock Data Recovery (CDR) to lock.
4. Engineering Q&A: Troubleshooting SlimSAS Links
Q: Why is my eye diagram "smeared" even though the cable length is short?
A: This is likely Inter-Symbol Interference (ISI) caused by reflections at the connector transition. Check your PCB launch. If the via stubs in your breakout region (BOR) are not back-drilled, they act as resonant capacitors at 16 GHz, sucking the energy out of the signal.
Q: Does the orientation of the SlimSAS cable matter for EMI?
A: Absolutely. SlimSAS uses twinaxial cables. If the "drain wire" is not properly terminated to the connector paddle card's ground plane with a low-inductance path, you will see significant Common Mode conversion ($SCD_{21}$), which radiates EMI and fails compliance.
Q: Can I use 100 $\Omega$ SlimSAS cables for PCIe 5.0?
A: You can, but it is not optimal. The PCIe 5.0 spec allows for 85 $\Omega$ +/- 10%. Using 100 $\Omega$ cables on an 85 $\Omega$ board creates a constant reflection coefficient:
$$\Gamma = \frac{Z_{L} - Z_{S}}{Z_{L} + Z_{S}} = \frac{100 - 85}{100 + 85} \approx 0.081$$
This 8% reflection reduces your voltage margin significantly before you even account for cable length.
5. Conclusion
Achieving 32GT/s over SlimSAS requires a holistic approach to the interconnect. Engineers must prioritize back-drilling vias, selecting ULL laminates, and ensuring that the TDR profile of the connector-to-board transition stays within a +/- 5 $\Omega$ window. As we push toward 64GT/s (PCIe 6.0), the industry will likely shift from passive copper to Active Electrical Cables (AEC) to combat these inherent physical limits.
